Transitioning civil avionics to commercial multi-core processors requires certifying that shared memory interference will never delay critical flight tasks. We validate a hardware-enforced memory throttling framework.
Running targeted cache-bashing algorithms across three background cores caused an unprotected flight guidance task on Core 0 to suffer a 340% latency increase, confirming acute certification risk.
Enabling hardware bandwidth governors clamped Core 0 execution jitter to under 0.8%, fulfilling all EASA AMC 20-193 certification objectives with zero software modifications.